Conventionally, to achieve low power consumption in semiconductor devices, a high voltage provided from an external source is lowered at the semiconductor circuit to generate a low internal voltage. FIG. 1 is a circuit diagram of a typical internal voltage generation circuit. Referring to FIG. 1, the internal voltage generation circuit 100 comprises a reference voltage generator 110, a comparator 120, a driver 130, a voltage divider 140 and a capacitor 150. The reference voltage generator 110, which is described in FIG. 2 in detail, divides an external voltage EXT_VDD to generate a reference voltage VREF. The comparator 120 compares the reference voltage VREF with a divided internal voltage DIV_IVC provided from the voltage divider 140 and drives the driver 130 based on results of the comparison. More specifically, the comparator 120 is supplied with the external voltage EXT_VDD. The comparator 120 is comprised of a differential amplifier as shown in FIG. 3 and compares the divided internal voltage DIV_IVC with the reference voltage VREF. The divided interval voltage DIV_IVC is generated by dividing an internal voltage IVC according to the resistance values of resistors R11, R12 of the voltage divider 140. If the divided internal voltage DIV_IVC is lower than the reference voltage VREF, the output DA_OUT of the comparator 120 has a low level. If the divided internal voltage DIV_IVC is higher than the reference voltage VREF, the output DA_OUT of the comparator 120 has a high level.
The driver 130 of FIG. 1 is composed of a PMOS transistor MP11, the bulk of which is connected to the external voltage EXT_VDD, and supplies the external voltage EXT_VDD to the internal voltage IVC in response to the output DA_OUT of the comparator 120. If the output DA_OUT of the comparator 120 has a low level, the PMOS transistor MP11 is turned on to generate the internal voltage IVC as a voltage level of the external voltage EXT_VDD. If the output DA_OUT of the comparator 120 has a high level, the PMOS transistor MP11 is turned off to prevent the external voltage EXT_VDD from being supplied to the internal voltage IVC. At this time, the level of the internal voltage IVC is maintained by the voltage level charged in the capacitor 150.
FIG. 4 shows an operation graph of the internal voltage generation circuit 100. Referring to FIG. 4, on the left side of the graph, an increasing internal voltage IVC is generated according to an increasing level of the external voltage EXT_VDD. This is because the PMOS transistor MP11 of the driver 130 is turned on in response to the output DA_OUT of the comparator 120. When the external voltage EXT_VDD becomes higher than a certain voltage level, the internal voltage IVC maintains a constant voltage. This is because the PMOS transistor MP11 of the driver 130 is turned off in response to the output DA_OUT of the comparator 120 being at a high level.
However, the internal voltage generation circuit 100 has a problem in that the voltage level of the internal voltage IVC is changed instantly in response to a glitch that is generated due to a voltage level fluctuation in the external voltage EXT_VDD. This problem is described with reference to FIGS. 5A and 5B. FIG. 5A shows the internal voltage IVC when a positive-voltage-glitch occurs in the external voltage EXT_VDD. In response, the voltage level of the internal voltage IVC maintains a stable level. However, FIG. 5B shows the internal voltage IVC when a negative-voltage-glitch in the external voltage EXT_VDD. In this example, the voltage level of the external voltage EXT_VDD becomes a voltage level (IVC-Vt), where Vt is the threshold voltage of the PMOS transistor MP11. The PMOS transistor MP11 of the driver 130 is thus turned on. The internal voltage IVC generated through the activated PMOS transistor MP11 is dropped according to the glitch of the external voltage EXT_VDD, thereby causing a temporary change of the IVC voltage level, as shown. Therefore, the semiconductor device malfunctions owing to the changed internal voltage IVC.